Measurement-computing Digital488 Uživatelský manuál stáhnout pdf (Strana 26)

Section 2 Getting Started

2.10

2.4.1 My Talk Address

(MTA)

When the

Digital488

is addressed to talk (

) it asserts

Inhibit

, reads

the data from all ports, un-asserts

Inhibit

and outputs the data to the bus in

the format as defined by the

and

commands. The output bus

terminators are appended to the output with the exception of the

and

formats.

does not append terminators. The output format of

will be

described separately. After output in the

through

formats, the

Digital488

must be re-addressed to talk to perform subsequent reads.

In the

mode, it will wait for the selected

EDR

transition before

reading the data and formatting it for output. If the

EDR

line has transitioned

prior to being addressed to talk, the data read at the time of

EDR

will be

buffered for output when next addressed to talk. If

EDR

transitions again

before the previous

EDR

buffered data has been output, the

Digital488

will

generate an

EDR Overrun

error and ignore the

EDR

read request. After

output in the

through

formats, the

Digital488

must be re-addressed to

talk to perform subsequent buffered output of

EDR

captured data.

In either

mode, the

Digital488

can send requested status (

)

without affecting the data ports or

Inhibit

. After the requested status is

output, the presently programmed

mode returns.

EDR

cannot be used to capture data in the high speed binary format

(

). When addressed to talk in this format it asserts

Inhibit

, reads the data

from all ports, un-asserts

Inhibit

and outputs the binary data to the bus with

EOI asserted on the fifth byte. When the last data byte is transferred, the data

is read again in anticipation of another data transfer. If

Inhibit

is used to

sequence external hardware, this line will pulse N+1 times; where N is the

number of total (5 byte) data transfers. In this format the

Digital488

does not

have to be re-addressed to talk to read the ports multiple times.

With all

formats, the data is output in a PORT5, PORT4, PORT3,

PORT2, PORT1 sequence.

1 2 ... 21 22 23 24 25 26 27 28 29 30 31 ... 82 83

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