Measurement-computing CIO-DAS6402/12 Uživatelský manuál stáhnout pdf (Strana 27)

Table 5-7. Comparison of Features: Compatible vs. Enhanced Mode

YesNoPre-trigger

Single ADC

REP INSW

End of Burst

External

Single ADC

DMA

Interrupts

YesYes Burst Mode

no, CTR0 used for pre-triggeringyes, CTR0Independent Counter at user

connector

yesnoREP INSW

noyesDMA

Separate from Trigger, uses DIN0Combined w/ Trigger on DIN1External Pacing

Separate from Pacing, uses DIN1.

Can be gate (level) or trigger

(edge)

Combined w/ Pacing on DIN1, gate

only

External Triggering

8 in

8 out

4 in

4 out

# Digital I/O

64 S-E

32 Diff

16 S-E

8 Diff

# Analog Input Channels

EnhancedCompatible

MODEFeature

In Enhanced mode, HC_AI1, HC_AI0 select the interrupt source, which also will determine the acquisition mode the board is to

be operated under. These bits are 0 in Compatible mode. Refer to Table 6-8.

Table 5-8. Interrupt Source Coding - Enhanced Mode

End of BurstBurst REP INSW ( 2-64 samples)11

FIFO ½ FullFifo REP INSW (512 samples)01

FIFO Not EmptySingle ADC interrupt10

noneSingle ADC polled 00

Interrupt SourceADC Acquisition Mode

HC_AI0HC_AI1

If pre-trigger is enabled, (allowed during a REP INSW mode, HC_AI1=1) then an End-of-Acquisition interrupt will be enabled.

This interrupt occurs a pre-determined number of conversions after the trigger. Counter 0 is programmed to count conversions after

the trigger and will cause the interrupt when it counts down and reaches Terminal Count.

GAIN1, GAIN0 select the front end gain (Table 5-9). They are valid for Enhanced or Compatible Mode.

Table 5-9. Front-End Gain Coding

0 to 1.25V or ±1.25V811

0 to 2.5V or ±2.5V401

0 to 5V or ±5V210

0 to 10V or ±10V100

Analog Input Voltage RangeAnalog Input Gain

GAIN0GAIN1

1 2 ... 22 23 24 25 26 27 28 29 30 31 32 ... 39 40

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